1. Technical Field
This invention generally relates to semiconductor devices and, more particularly, to semiconductor devices that isolate a photodiode in a solid-state image sensor to lower junction leakage to thereby improve image quality.
2. Background
Complementary metal oxide semiconductor (CMOS) technology has made significant strides in competing with charge coupled device (CCD) technology as the solid-state image sensor of choice for use in various applications such as stand-alone digital cameras and digital cameras embedded in other imaging devices (e.g., cellular phones and personal digital assistants). The principle advantages of CMOS sensor technology are lower power consumption, higher levels of system integration and the ability to support very high data rates.
To remain competitive, CMOS technology must improve in various areas, including the area of image quality. One source of image quality problems is known as “dark current” from junction leakage in a reverse-biased photodiode used in CMOS image sensors. Junction leakage remains a problem in sub-micron CMOS process technology since this technology has generally not been optimized for low junction leakage, but rather has been optimized for digital logic speed. This optimization for high switching speed results in shallow source/drain junctions that have higher junction leakage. Thus, imager devices have been typically constructed in a process technology that was originally optimized for digital logic, not low junction leakage. In the image sensor area, the leakage of charge from a reverse-biased photodiode is conventionally known as “dark current” since the charge leakage produces a signal in the absence of light. When this dark current is too high, the variance in the dark current degrades image quality and can also limit the maximum integration time for light collection. There is therefore a need to reduce the dark current in the CMOS fabrication process for forming image sensors.
One source of dark current is from the shallow trench isolation process methods for typical CMOS logic and analog process flows that have not yet been optimized for extremely low reverse bias junction leakage. As is well known in the art, shallow trench isolation is used for various metal oxide semiconductor circuits to address common problems associated with standard LOCOS isolation (e.g., bird's beak problems where oxide grows under the edge of the blocking silicon nitride layer to increase the size of the semiconductor device). In standard shallow trench isolation, a shallow trench is etched between elements in a semiconductor and filled with a deposited dielectric. After sidewall oxidation and dielectric fill of oxide, a CMP step typically occurs.
The source of the dark current in shallow trench isolation methods for typical CMOS process flows usually stems from damage to the silicon surface that occurs during etching of the shallow trench. This damage increases the density of traps and other imperfections in the silicon substrate and causes increased junction leakage, which, in turn, degrades image quality in CMOS image sensors. CMOS imagers perform best if the junction leakage is very low and preferably less than 2.0×10−17 amps per pixel. Standard methods can result in reverse bias junction leakage which are one or two orders of magnitude higher than the goal for CMOS imagers.
A need therefore exists to reduce reverse-bias junction leakage to levels suitable for high performance imaging applications using the CMOS sensor. This solution also should be easily integrated in a common CMOS process flow with little additional manufacturing costs.